The present invention relates to semiconductor devices and methods of operating the same. More specifically, the present invention is directed to non-volatile memory devices and methods of operating the same.
Semiconductor memory devices require various characteristics such as high speed operation, low power dissipation, random access, and high capacity storage determined according to devices and systems in which they are applied. Among non-volatile memory devices, a 2-transistor FN tunneling type EEPROM cell has an array structure which is able to write/erase byte data. Therefore, the 2-transistor FN tunneling type EEPROM cell is being widely used as a data access type and data storage type memory device.
A unit cell of an EEPROM cell includes a memory cell transistor and a selection transistor. Accordingly, the EEPROM cell has disadvantages such as a larger area occupied by the unit cell and a lower integration density than a flash memory device. Similar to a flash memory device, an FN tunneling type EEPROM cell includes a FLOTOX-type memory cell transistor and has a structure in which a selection transistor is serially connected to the FLOTOX-type memory cell transistor. Conventionally, a memory cell transistor and a selection transistor are different in channel length, and a portion of a gate insulator of the memory cell transistor has a tunnel insulator structure.
In recent years, an EEPROM cell has been introduced in which a memory cell transistor and a selection transistor have a minimum-sized channel length to enhance an integration density. However, a conventional EEPROM cell experiences leakage current and increased resistance caused by a common source region because the common source region and a drain region are different in configuration.